This invention relates to a memory device operable at a high speed and a memory system comprising a plurality of memory systems of the type.
Recently, memory devices are highly integrated while an interface for operating the memory devices at a high speed and with a low signal amplitude is developed. As a standard for such interface, proposal is made of SSTL (Stub Series Termination Logic). In order to operate a DRAM (Dynamic Random Access Memory) as one of memory devices at a high speed, proposal is also made of a DDR (Double Data Rate) solution in which a data rate can be doubled by carrying out data input/output in synchronism with both of leading and trailing edges of each clock.
A memory system for carrying out the above-mentioned operation has a structure in which a plurality of memory modules are arranged on a mother board in parallel to one another with a space left from one another. In this case, the memory modules are mounted on the mother board through a plurality of connectors, respectively. In order to fix each memory module to the mother board, each connector has a slot to receive the memory module. In each slot, a plurality of terminals pl are arranged for electrical connection with the memory module. On the other hand, the memory module is provided with a plurality of memory devices and a plurality of buffers, such as registers, mounted on a front side and/or a back side thereof. The memory devices and the registers are electrically connected to the connectors through a plurality of terminals formed on an end portion of the memory module.
One of memory systems of the type further comprise a controller, called a chip set, mounted on the mother board to control the memory devices on the memory modules. In this memory system, a data bus, a command address bus, and a clock bus (in the following description, these buses may collectively and simply be called a bus) are arranged on the mother board. Through these buses, the controller is electrically connected to the memory devices and the registers on the memory modules.
For example, the above-mentioned buses are connected in the following manner. The data bus and the clock bus from the controller are directly connected to the memory devices on the memory modules. On the other hand, the command address bus is connected through the registers to the memory devices on the memory modules.
Furthermore, a memory system according to the SSTL standard has a structure in which DRAM's as memory devices in each memory module are connected to a connector through stubs pl. As a specific example, disclosure is made of a memory system in which DRAM's as memory devices are mounted on both sides of a memory module fitted to a slot of a connector. The DRAM's mounted on the both sides of the memory module are connected to a data bus through stubs.
For the memory system of the type, it is considered to supply a clock bus with clocks having a frequency of 100 MHz or more (for example, 133 MHz) in order to perform input/output at a higher speed. In this case, the data rate upon reading/writing is not lower than 200 MHz if the DDR is adopted. Recently, it is required to operate each memory module at a clock frequency of 200 to 400 MHz. In this case, the data rate is as high as 400 to 800 MHz.
Referring to FIG. 1, description will be made of a related memory system. The memory system illustrated in the figure comprises a memory controller 21 mounted on a mother board (not shown), a plurality of memory modules 201 and 202 fitted to a plurality of slots (not shown) on the mother board, a clock generator 101 for generating write clocks, and a clock generator 102 for generating read clocks Each of the memory modules 201 and 202 mounted on the mother board is provided with a plurality of DRAM's. In each slot, a connector (not shown) is arranged. In the illustrated example, the DRAMf and the DRAMr are arranged on front and back sides of each memory module, respectively. Each of the DRAMf and the DRAMr is connected through stubs on the connector and the memory module to a data bus DB, a command address bus CB, a write clock bus WB, and a read clock bus RB.
Each bus is branched on the memory module so as to be connected to the DRAMf and the DRAMr formed on the front and the back sides of each of the memory modules 201 and 202. In the illustrated example, the command address bus CB includes a control signal line for transmission and reception of a termination control signal. The write clock bus WB is supplied with the write clocks from the clock generator 101. On the other hand, the read clock bus RB is supplied with the read clocks from the clock generator 102. The memory controller 21 is connected to each of the DRAMf and the DRAMr through the data bus DB and the command address bus CB.
The memory system being illustrated has a large capacity and is operable at a high speed. As shown in the figure, in the memory system, one end of the data bus DB is connected to the controller 21. On the other hand, the other end, i.e., a far end of the data bus DB is connected to a termination resistor (not shown) as a terminating element. The termination resistor is applied with an electric voltage from a termination power supply (not shown). However, in the above-mentioned memory system in which the DRAM's are connected to the data bus DB branched at each connector and at each stub, termination only at the far end of the data bus DB brings about unnegligible deterioration of the signal quality due to signal reflection resulting from mismatching of wiring impedance of the data bus DB. Therefore, it is found out that the above-mentioned termination scheme can not cope with the memory system operable at a high speed.